1. Field of the Invention
The invention relates to alignment substrates upon which extended arrays of discrete (silicon wafer) subunits (or chips) can be assembled into full width arrays The invention also relates to methods of making these alignment substrates and methods of using same. The invention can be used with or without vacuum hold-down structures for maintaining the position of the subunit.
2. Description of Related Art
With the increased interest in rastor scanners, both to read and write images, has come renewed demand in the art for an economical full width scanning array. In the current stage of scanner technology, the art is without a commercially acceptable and economically feasible method of producing very long unitary scanning arrays, that is, single arrays of sufficient linear extent and with the requisite number of image processing elements to scan an entire line at once with a high image resolution. In this context, when speaking of scanning arrays, there are both image reading arrays which comprise a succession of image sensing elements to convert the image line to electrical signals or pixels, and image writing arrays which comprise a succession of light producing or other elements employed to produce images in response to an image signal or pixel input.
The prior art has faced this failure or inability to provide long full width scanning arrays with various proposals. These include optical and electrical arrangements for overlapping plural shorter arrays and abutting short arrays together in end-to-end arrangements. However, none of these proposals has met with any great degree of success. For example, in the case of abutting smaller arrays together, due to the difficulty of exactly aligning and mating the array ends with one another, losses and distortion of the images often occur.
A similar problem arises with thermal ink jet printheads. Thermal ink jet printheads are fabricated by using silicon wafers and processing technology to make multiple small heater plates and channel plates. This works extremely well for small printheads. However, for large array or pagewidth printheads, a monolithic array of ink channels or heater elements cannot be practically fabricated in a single wafer since the maximum commercial wafer size is six inches. Even if ten inch wafers were commercially available, it is not clear that a monolithic channel or heater array would be very feasible. This is because only one defective channel or heater element out of 2,550 channels or heater elements would render the entire channel or heater plate useless. This yield problem is aggravated by the fact that the larger the silicon ingot diameter, the more difficult it is to make it defect free. Also, relatively few 81/2 inch channel plate arrays could be fabricated in a ten inch wafer. Most of the wafer would be thrown away, resulting in very high fabrication costs. Thus, there is also the need in the field of thermal ink jet printhead fabrication for a method of forming extended arrays of silicon wafer subunits.
Stoffel et al U.S. Pat. No. 4,690,391 discloses a method and apparatus for fabricating long full width scanning arrays for reading or writing images. For this purpose, smaller scanning arrays are assembled in abutting end to end relationship, each of the smaller arrays being provided with a pair of V-shaped locating grooves in the face thereof. An aligning tool having predisposed pin-like projections insertable into the locating grooves on the smaller scanning arrays upon assembly of the smaller arrays with the aligning tool is used to make a series of the smaller arrays in end to end abutting relationship, there being discretely located vacuum ports in the aligning tool to draw the smaller arrays into tight face-to-face contact with the tool. A suitable base is then affixed to the aligned arrays and the aligning tool withdrawn. A limitation with the tool of Stoffel et al is that the accuracy of the extended array is a function of the accuracy with which the alignment structures can be formed on the tool. The present invention is an improvement over the method disclosed by U.S. Pat. No. 4,690,391.